Job Description
Responsibilities:
Develop and enhance timing analysis/signoff work flow from frontend (pre-layout) to backend (post-layout) at both chip and block level.
Chip level Integration, physically partitioning and floor planning.
Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic <-> IO macros interfaces such as PCI-E, Frame-Buffer/Memory, HDMI, etc.
Design optimization and timing convergence related tasks.
Development of PD work flows.
Qualifications:
BS or MS in Electrical Engineering or Computer Science, or equivalent experience.
3+ years of relevant ASIC design experience ideally with a focus in timing.
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